Automatic low-cost IP watermarking technique based on output mark insertions

International audienceToday, although intellectual properties (IP) and their reuse are common, their use is causing design security issues: illegal copying, counterfeiting, and reverse engineering. IP watermarking is an efficient way to detect an unauthorized IP copy or a counterfeit. In this context, many interesting solutions have been proposed. However, few combine the watermarking process with synthesis. This article presents a new solution, i.e. automatic low cost IP watermarking included in the high-level synthesis process. The proposed method differs from those cited in the literature as the marking is not material, but is based on mathematical relationships between numeric values as inputs and outputs at specified times. Some implementation results with Xilinx Virtex-5 FPGA that the proposed solution required a lower area and timing overhead than existing solutions

Amélioration du processus de vérification des architectures générées à l'aide d'outils de synthèse de haut-niveau

L'augmentation de la capacité d'intégration des circuits a permis le développement des systèmes de plus en plus complexes. De cette complexité sont nés des besoins conséquents quant aux méthodes de conception et de vérification. Les outils de synthèse de haut-niveau (HLS) sont une des réponses à ces besoins. Les travaux présentés dans cette thèse ont pour cadre l'amélioration du processus de vérification des architectures matérielles synthétisées par HLS. En particulier, ils proposent une méthode pour la transformation des assertions booléennes spécifiées dans la description algorithmique d'une application en moniteurs matériels pour la simulation. Une deuxième méthode est proposée. Elle cible la synthèse automatique d'un gestionnaire d'erreurs matériel dont le rôle est d'archiver les erreurs survenant dans un circuit en fonctionnement réel, ainsi que leurs contextes d'exécution.The fast growing complexity of hardware circuits, during the last three decades, has change devery step of their development cycle. Design methods evolved a lot, and this evolutionwas necessary to cope with an always shorter time-to-market, mainly driven by the internationalcompetition.An increased complexity also means more errors, harder to find corner-cases, and morelong and expensive simulations. The verification of hardware systems requires more andmore resources, and is the main cost factor of the whole development of a circuit. Since thecomplexity of any system increases, the cost of an error undetected until the foundry stepbecame prohibitive. Therefore, the verification process is divided between multiple stepsinvolved at every moment of the design process : comparison of models behavior, simulationof RTL descriptions, formal analysis of algorithms, assertions usage, etc. The verificationmethodologies evolved a lot, in order to follow the progress of design methods. Somemethods like the Assertion-Based Verification became so important that they are nowwidely adopted among the developers community, providing near-source error detection.Thus, the work described here aims at improving the assertion-based verification process,in order to offer a consequent timing improvment to designers. Two contributions aredetailed. The first one deals with the transformation of Boolean assertions found in algorithmicdescriptions into equivalent temporal assertions in the RTL description generatedby high-level synthesis (HLS) methodologies. Therefore, the assertions are usable duringthe simulation process of the generated architectures. The second contribution targets theverification of hardware systems in real-time. It details the synthesis process of a hardwareerror manager, which has to save and serialize the execution context when an error isdetected. Thus, it is easier to understand the cause of an error and to find its source. Theerrors and their contexts are serialized as reports in a memory readable by the system ordirectly by the designer. The behavior of a circuit can be analyzed without requiring anyprobe or integrated logic analyzer.BORDEAUX1-Bib.electronique (335229901) / SudocSudocFranceF

Beyond Gbps Turbo Decoder on Multi-Core CPUs

International audienceThis paper presents a high-throughput implementation of a portable software turbo decoder. The code is optimized for traditional multi-core CPUs (like x86) and it is based on the Enhanced max-log-MAP turbo decoding variant. The code follows the LTE-Advanced specification. The key of the high performance comes from an inter-frame SIMD strategy combined with a fixed-point representation. Our results show that proposed multi-core CPU implementation of turbo-decoders is a challenging alternative to GPU implementation in terms of throughput and energy efficiency. On a high-end processor, our software turbo-decoder exceeds 1 Gbps information throughput for all rate-1/3 LTE codes with K < 4096

Design Space Exploration for Partially Reconfigurable Architectures in Real-Time Systems

International audienceIn this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints, enabling Design Space Exploration (DSE) at the early stages of the development. FoRTReSS can be completely integrated into existing partial reconfiguration flows to generate physical constraints describing the architecture in terms of reconfigurable regions that are used to floorplan the design, with key metrics such as partially reconfigurable area, real-time or external fragmentation. The flow is based upon our SystemC simulator for real-time systems that helps develop and validate scheduling algorithms with respect to application timing constraints and partial reconfiguration physical behaviour. We tested our approach with a video stream encryption/decryption application together with Error Correcting Code and showed that partial reconfiguration may lead to an area improvement up to 38% on some resources without compromising application performance, in a very small amount of time: less than 30 s

Energy Consumption Analysis of Software Polar Decoders on Low Power Processors

International audienceThis paper presents a new dynamic and fully generic implementation of a Successive Cancellation (SC) decoder (multi-precision support and intra-/inter-frame strategy support). This fully generic SC decoder is used to perform comparisons of the different configurations in terms of throughput, latency and energy consumption. A special emphasis is given on the energy consumption on low power embedded processors for software defined radio (SDR) systems. A N=4096 code length, rate 1/2 software SC decoder consumes only 14 nJ per bit on an ARM Cortex-A57 core, while achieving 65 Mbps. Some design guidelines are given in order to adapt the configuration to the application context

Séquenceur mémoire pour applications multimédias temps réel gérant les séquences d'accès indéterministes

Dans le domaine du traitement du signal et de l'image, les applications multimédias sont souvent caractérisées par un grand nombre d'accès aux données. Pour la plupart de ces applications, les accès aux données structurées (tableaux, vecteurs) sont réguliers et périodiques. Dans ces conditions, il est possible et efficace de générer des contrôleurs pipeline d'accès à la mémoire. Cette technique est utilisée afin d'améliorer les accès en mode pipeline autorisés par les mémoires actuelles. On utilise pour cela des composants matériels dédiés pour générer les adresses et pour packer/dépacker les données. Dans cet article nous présentons l'architecture d'un séquenceur mémoire qui permet de prendre en compte de manière efficace les accès prédictibles aussi bien que les séquences d'accès non prédictibles (calculs d'adresses dynamiques) de manière pipeline

An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes

International audienceError Correction Code decoding algorithms for consumer products such as Internet of Things (IoT) devices are usually implemented as dedicated hardware circuits. As processors are becoming increasingly powerful and energy efficient, there is now a strong desire to perform this processing in software to reduce production costs and time to market. The recently introduced family of Successive Cancellation decoders for Polar codes has been shown in several research works to efficiently leverage the ubiquitous SIMD units in modern CPUs, while offering strong potentials for a wide range of optimizations. The P-EDGE environment introduced in this paper, combines a specialized skeleton generator and a building blocks library routines to provide a generic, extensible Polar code exploration workbench. It enables ECC code designers to easily experiments with combinations of existing and new optimizations , while delivering performance close to state-of-art decoders

Zebra : Building Efficient Network Message Parsers for Embedded Systems

4 pagesInternational audienceSupporting standard text-based protocols in embedded systems is challenging because of the often limited computational resources that embedded systems provide. To overcome this issue, a promising approach is to build parsers directly in hardware. Unfortunately, developing such parsers is a daunting task for most developers as it is at the crossroads of several areas of expertise, such as low-level network programming, or hardware design. In this paper, we propose Zebra, a generative approach to drastically ease the development of hardware parsers and their use in network applications. To validate our approach, we have used Zebra to generate hardware parsers for widely used protocols, namely HTTP, SMTP, SIP, and RTSP. Our experiments show that Zebra-based parsers are up to 11 times faster than software-based parsers

Fast Simulation and Prototyping with AFF3CT

International audienceThis demonstration intends to present AFF3CT (A Fast Forward 3rror Correction Tool). The main objective of AFF3CT is to provide a portable, open source, fast and flexible software to the channel coding community in such a way that researchers can spend more time on channel coding / algorithmic problems instead of software development issues. It is also intended to facilitate the process of hardware verification and debug with the objective of fast prototyping. I. SIMULATION OF A DIGITAL COMMUNICATION CHAIN Despite the wide variety of existing communication systems , all of them are based on a common abstract model that was proposed by the genius founder of information theory, Claude Shannon [1]. Figure 1 shows the synoptic of such a communication chain. In this structure, the channel encoder and decoder determine the achievable error rate of the system. Moreover, the channel decoder is a large contributor in the overall computational complexity of the system. On the eve of the 5th generation of mobile communication systems, one of the challenges is to imagine systems able to transmit a huge amount of data in a very short amount of time at a very small energy cost in a wide variety of environments. In such a context, researchers work at refining some existing coding schemes (encoder + decoder) in such a way that the system has a low residual error rate and that the associated decoder is fast, flexible and has a low complexity. The validation of a new coding scheme requires the estimation of the error rate performance. Unfortunately, most of the time, no simple mathematical model exists to predict the performance of a channel encoder/decoder. The only simple solution is to perform a Monte Carlo simulation of the whole communication chain: some data are pseudo-randomly generated, encoded, modulated, noised, decoded and the performance is estimated by measuring the Bit Error Rate (BER) and the Frame Error Rate (FER) at the receiver side. This apparently simple setup leads to three main problems. Reproducibility: It is usually a tedious task to reproduce the results from the literature. This can be explained by the large amount of empirical parameters necessary to define one communication system and not all of them are reported in the publications. Moreover, it is rare that researchers actually share the source code of their simulator. As a consequence, a large amount of time is spent "reinventing the wheel" only to be able to compare to the state-of-the-art results

AFF3CT : Un environnement de simulation pour le codage de canal

International audienceDans cet article nous présentons un environne-ment de simulation de Monte Carlo pour les systèmes de communications numériques. Nous nous focalisons en particulier sur les fonctions associées au codage de canal. Après avoir présenté les enjeux liés à la simulation , nous identifions trois problèmes inhérents à ce type de simulation. Puis nous présentons les princi-pales caractéristiques de l'environnement AFF3CT